| 摘要 |
PURPOSE:To avoid the distribution of an exclusive address bus and To eliminate the need for excess cycle time by using the swap system when a multi-copy bit is reset and using the store-through system when set so as to apply operand storage. CONSTITUTION:A CPU-A loads one block to a cache memory 11 from a main storage device MS 20 at the corresponding block. In this case, the storage of the swap system is selected by a swap/store-through decision circuit 6 and a write C-bit of said block is set to '1'. In executing the store by the CPU-A, since a multi-copy MC bit 21 of a tag memory of the CPU-A is at '1', the storage by the store-through system is decided by the swap/store-through decision circuit 6.
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