发明名称 TEST SYSTEM FOR INFORMATION PROCESSOR
摘要 PURPOSE:To allow other functions including a leading control function to detect the error of a computing element and to easily pinpoint a troubled place by permitting a simulator to execute a random test program from the leading control valid status and leading control invalid status of an information processor to be tested and comparing the executed results. CONSTITUTION:A test processor 1 has the 1st memory 3 and the 1st insstruction processing part 5. The 1st main memory 3 stores a random test task 10 including a random test program generation means 11, a random test program activation means 12, an execution result decision means 13 and the simulator 14, and an operating system 30. The simulator 14 has the 3rd main memory 15 and the 3rd instruction processing part 17. The 3rd main memory 15 stores the 2nd random test program 16. The 2nd main memory 4 has a random test program execution area 41, a random test program initial value area 42, an execution result area 43 for the leading control valid status, an execution result area 44 for the leading control invalid status and a random test program control sequence execution area 45.
申请公布号 JPS62203240(A) 申请公布日期 1987.09.07
申请号 JP19860045404 申请日期 1986.03.04
申请人 NEC CORP 发明人 NISHIOKA HIROSHI
分类号 G06F11/22 主分类号 G06F11/22
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