发明名称 PEAK HOLDING CIRCUIT
摘要 PURPOSE:To obtain an accurate peak voltage value by nearly equalizing the peak voltage at an output terminal to the base voltage of a 1st transistor (TR). CONSTITUTION:A peak voltage from a buffer circuit is inputted to the base of the 1st TR 17 and then the collector-base voltage becomes almost zero, so that a collector leak current is reduced. When the 2nd TR 19 is turned off, a reverse bias is applied between the base and emitter of the TR 17, which does not turn on. When a reset signal is inputted from a terminal 21, the TR 19 turns on and the emitter of the TR 17 is at nearly the same potential with the collector of the TR 19, so the reverse bias is removed and the TR 17 also turns on. Consequently, charges in a capacitor 13 depending upon an input signal are discharged to a terminal 20 through the TRs 17 and 19 and the peak voltage at a terminal 15 also drops. Therefore, while the reset signal is not inputted to the terminal 21, the TRs 17 and 19 are turned off and the collector- base voltage of the TR 17 is almost zero, so the flowing of the collector leak current to the TR 17 is suppressed and the accurate peak voltage is held for a long period.
申请公布号 JPS62201370(A) 申请公布日期 1987.09.05
申请号 JP19860043745 申请日期 1986.02.28
申请人 ANRITSU CORP 发明人 KASHIWAGI TOSHIHIRO
分类号 G01R19/04;H03K6/00 主分类号 G01R19/04
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