| 摘要 |
PURPOSE:To reduce parasitic resistance, to prevent the deterioration of voltage resistance of a gate and, moreover, to check an increase in gate capacity, by forming a gate electrode only in a part wherefrom a high concentration layer is removed, so that it is separated by an insulator from the high concentration layer formed on the upper side of an active layer. CONSTITUTION:A gate electrode 1 connecting to an active layer 12 of a field effect transistor is formed only in a part wherefrom a high concentration layer 13 is removed, so that it is separated by an insulator 4 from the high concentration layer 13 formed on the upper side of the active layer 12. When this method is applied to GaAs MESFET, for instance, the insulator 4 is formed only on the lateral wall of an N<+> GaAs cap layer 13, and a gate metal 1 is formed only inside a recess structure. Between the N<+> GaAs layer 13 and the gate metal 1, according to this method, there is only a parasitic resistance in an opened portion set by the film thickness of the lateral wall 4 of the insulator, and since this resistance is very small, no increase in parasitic resistance occurs. Moreover, there is no deterioration in the voltage resistance of a gate, since the gate metal 1 and the N<+> GaAs layer 13 are separated from each other by the side wall insulator 4. In addition, there is also no increase in a source-gate capacity, since the gate metal is formed only inside the recess structure.
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