| 摘要 |
PURPOSE:To reduce an area occupied by a memory cell while keeping the capacity of an MOS capacitor large sufficiently and thereby to enable the attainment of a memory device of high density, by utilizing the lateral side of an insular region as the MOS capacitor of the memory cell, and by forming a gate electrode from the upper side of a substrate down to the lateral side. CONSTITUTION:A capacitor having a capacitor electrode 16 buried in a groove of an element-isolating region is provided except for the upper side of the groove, a gate electrode 18 of MOS-type FET is provided from the upper side of a substrate in an element region down to the lateral side of the groove, and a reverse conductivity type layer 20 connecting to a bit wire 21 is provided adjacently to the gate electrode 18 on the upper side of the substrate. For instance, grid-shaped grooves are formed in a P-type silicon substrate 11 to form a plurality of insular regions 13, and P-type layers 14 for preventing inversion are formed. Next, first gate oxide films 15 are formed, and phosphorus-doped polycrystalline silicon is deposited to form capacitor electrodes 16. Then after second-layer polycrystalline silicon doped with phosphorus through second gate oxide films 17 is deposited to form gate electrodes 18, the whole surface is covered with an oxide film 19, contact holes are opened, and n<+> layers 20 to operate as drains of MOS transistors and an Al wiring 21 are formed. |
