| 摘要 |
PURPOSE:To prevent the DC potential fluctuation between on input and output and the occurrence of a lowering of gain by providing a capacitor between a holding circuit and a buffer circuit to obtain an output signal voltage from which the offset voltage of the buffer circuit is eliminated. CONSTITUTION:When switches 2, 10, and 11 are turned ON during a sampling cycle, a signal from an input terminal 1 is held in a capacitor 3. The signal further is supplied to a transistor 6 so that a voltage that is a voltage made by lowering a signal potential by an offset voltage VGS appears in the source, which is held in the capacitor 5. Next, when the switches 2, 10, and 11 are turned OFF and a switch 4 is turned ON, the voltages held in the capacitors 3, 5 are supplied to the gate of the transistor 6, and the potential made by lowering the signal potential by the voltage VGS is outputted to an output terminal 9. As a result, the sample holding can be executed without the risk of the DC potential fluctuation between the input and the output or the lowering of gain.
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