| 摘要 |
PURPOSE:To reduce jitter of the extracted timing by applying suppress control of phase deviation even at a time section not receiving a reception pulse train. CONSTITUTION:The reception pulse train (b) is inputted to a time section discrimination section 13, where the time sections of T1, T2 are discriminated. A phase comparator 9 applies the phase comparison between a clock of frequency f0 being the 1/N frequency division of a frequency fm from an oscillator 7 by a variable frequency divider 8 and the changing point of the received pulse train (b) to detect phase lag/lead in a digital phase locked loop (DPLL) and the frequency division rate of the variable frequency divider 8 is controlled according to the detected information 10. An up-down counter 15 reset to the initial state by the end time information 14 of the time section T2 outputted from a time section discrimination section 13 increments its count at each detection of phase lead detection information of the information 10 and decrements its count at each phase lay detection information. |
