| 摘要 |
PURPOSE:To enhance the processing speed of CPU when data receiving bit shift is developed to the continuous address on RAM, by mounting an address means, an indication means, a shift means, a memory means and an OR means. CONSTITUTION:The counter 20 and timing generating circuit 1 of an address means, the data bus 10 and latch circuit 8 of an indication means, the bit shift circuit 9 and timing generating circuit 10 of a shift means, the latch circuit 11 of a memory means and the OR circuit 12 of an OR means are mounted to a memory reading/writing circuit. When n-bites of data are continuously subjected to bit shift to be developed on the address of RAM, RAM had to be access at least 2n-times usually but the number of access times to the RAM comes to (n+1) times. Therefore, the access of the RAM can be suppressed to the min. Because the number of access times of the RAM as observed from CPU comes to n-times, a processing speed can be enhanced markedly.
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