| 摘要 |
<p>In a multiprocessor data processing system, the sequential access portion (31b) of a memory (31) associated with one processor (P1) is connected to the sequential access portion (41b) of a memory (41) associated with another processor (P2) in such a way, via driver/receivers (34, 44) and a channel (51a), that data can flow between the sequential access portions asynchronously of the remainder of the system. Each of the memories (31, 41) also comprises a random access portion (31a, 41a) which is accessible by its associated processor via a conventional random access port and means to transfer data between its random access portion and its sequential access portion. Data flow operations between the sequential access portions of the memories is controlled by control means (32, 42) connected to the channel and via system buses (33, 43) to the processors (P1, P2).</p> |
