发明名称 MEMORY WRITING AND ERASING DEVICE
摘要 <p>PURPOSE:To prevent an erroneous writing/erasing by performing the erasing/ writing when a coincident state with a specified code is obtained, in a data updating time. CONSTITUTION:At the time of data updating of an EEPROM, an address signal is supplied to an address bus 2, then an access is performed to a specified code storage area 6. The storage area 6 outputs the specified code information stored in advance to a comparator circuit 7. Next, the same data as the specified code is supplied to a data bus 3, and the contents of both data are compared at the comparator circuit 7, and in a state where a coincident detection is completed, a charge pump circuit 5 is set at an enable state, and a high voltage Vpp is generated, then being entered to a waiting state. After wards, the data bus 3 and the address bus 2 are set at requested values to perform the updating, and the data updating of the area 3 in the EEPROM is performed. In this way, the cases of the erroneous writing/erasing can be considerably reduced.</p>
申请公布号 JPS62197995(A) 申请公布日期 1987.09.01
申请号 JP19860040941 申请日期 1986.02.24
申请人 SHARP CORP 发明人 ISHITSUKI NORIYOSHI;SAITO HITOSHI
分类号 G11C17/00;G06F21/24;G11C16/02 主分类号 G11C17/00
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