| 摘要 |
PURPOSE:To avoid the time loss and then malfunctions when the handshake or incorporation is carried out with an asynchronous logic circuit, by leading the signal inputted to an input terminal to a clear terminal and transmitting a partial state to the asynchronous logic. CONSTITUTION:A host logic circuit 1 confirms both ACKphi and ACK1 and waits until these ACKs become (L) level if they are (H) level while an STB is made (L) level if they are (L) level. On the other hand, main logic circuit 2 raises both ACKphi and ACK1 to (H) level when the STB is (H) level and waits until the STB becomes (L) level. Then the circuit 1 lowers the STB to (L) level after confirming both ACKs are (H) level. In this case, ACK1 falls to (L) level in synchronism with the fall of the STB not with the clock since an input terminal of a D type flip-flop 5 is connected to a clear terminal. In such a way, the working time of the ACKphi is shorter than that of the ACK1 and therefore the faster response is possible. |
