| 摘要 |
PURPOSE:To reduce the number of word lines by half while utilizing the advantages of a holding bit line system by arranging memory cells on some well regions in a matrix state, and varying the well potentials. CONSTITUTION:Some P-well Well1, Well2 are formed on an N-type semiconductor substrate. Some memory cells connected with several bit lines BL0-BLn-1 are arranged in the P-well Well1 in a matrix state. Some memory cells connected with dummy bit line BL0-BLn-1 through sense amplifiers S/A from the memory cells are similarly arranged to the P-well Well2 in a matrix state. A well potential is varied, a substrate bias effect is utilized, and a P-well potential formed with the memory cell connected with the BL lines is reduced to be selectively accessed. |
