| 摘要 |
PURPOSE:To detect a fault by allowing a signal processor having a designated address, and the (N+1)-th signal processor prepared for detecting a fault to execute the same operation by a reset signal, and comparing the contents of RAMs with each other. CONSTITUTION:In order to detect the fault of a signal processor 1, an address bus on a signal line 20 is set to '0'. In this case, a reset signal on a signal line 70 is inputted to only the signal processor 1 and a signal processor 5, and it is disregarded by other signal processors 2-4. In the signal processor, after being reset, if input signals are the same, the same operation is executed. Accordingly, the same signal as that of the signal processor 1 is inputted to the signal processor 5 added for detecting a fault, the contents of internal RAMs of the respective signal processors are outputted to signal lines 90, 100, they are inputted to an exclusive OR gate 6, and if output signals on the signal line 100 are all '0', it can be decided that the signal processor 1 is executing a normal operation. |
