| 摘要 |
PURPOSE:To ensure the highly accurate working of a comparator even in a high-speed action mode by cascading comparators at plural stages to set the load resistance of the comparator of the 1st stage at the input side at <=2/3 load resistance of the comparators at and after the 2nd stage and reducing the time constant of the comparator at the input side. CONSTITUTION:The resistance values 40 and 41 of a comparator 100 of the 1st stage are set at <=2/3 resistance value of load resistances 42 and 43 or a comparator 200 of the 2nd stage. While the resistances 42 and 43 of the comparator 200 are set at large resistance values to secure the standard voltage amplitude. In other words, the resistance values of resistances 40 and 41 are reduced for reduction of the time constant. Thus the discharge section, i.e., the hysteresis width is reduced and therefore the accurate output signal is obtained even with the clock signal of a high frequency.
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