发明名称 ADDRESS SIGNAL GENERATING CIRCUIT OF RAM
摘要 PURPOSE:To form an address signal generating circuit of a RAM, which is suitable for an IC conversion, by providing two adding circuits and a comparing circuit. CONSTITUTION:The titled circuit is constituted so that a block address can be determined by comparing an output of the first adding circuit 5 by a comparing circuit 7, and adding a value determined by its result and an output value of the first adding circuit 5 by the second adding circuit 11. In this way, this circuit is suitable for an IC conversion by a simple circuit constitution. That is to say, an address signal of a RAM can be generated by such a simple circuit constitution as the addition is executed by two adding circuits 5, 11, and also, it an correspond to both data series of right-down and left-down, and at the time of the IC conversion, its practical effect is high.
申请公布号 JPS62196750(A) 申请公布日期 1987.08.31
申请号 JP19860038844 申请日期 1986.02.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KIHARA NOBUYOSHI
分类号 G06F12/16;G11B20/12;G11B20/18 主分类号 G06F12/16
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