| 摘要 |
PURPOSE:To designate a fault part by providing N pieces of signal processors, the (N+1)-th signal processor, and an exclusive OR gate. CONSTITUTION:A control terminal 70 is made to enable, and this data is written in the internal RAM of a signal processor 5. In the signal processor, when the contents of the internal RAM are set to the same, the same operation is executed as long as the same input comes in thereafter. Accordingly, the same signal as that of a signal processor 1 is inputted to the signal processor 5 added for the purpose of detecting a fault, the contents of the internal RAMs of the respective signal processors are outputted to signal lines 90, 100, they are inputted to an exclusive OR gate 6, and when output signals on the signal line 100 are all '0', it can be decided that the signal processor 1 is executing a normal operation. At the time of detecting the fault of signal processors 2-4, it can be executed by setting an address bus 20 to 1-3, respectively and executing the same operation. |
