发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PURPOSE:To improve a read margin by providing the second load MOSFET selectively supplying a part of the read current for a selected memory cell in parallel connection with a load MOSFET to supply the said read current, so as to lift an operational ceiling voltage. CONSTITUTION:When a selected memory cell is in a high threshold voltage (logic '0') in comparison with the selection level of a word line, the output voltage Vs of an initial-stage amplifier circuit is determined solely according to the conductances ratios of a MOSFETQ12, an amplifying MOSFETQ11, a Y-gate MOSFET and the memory cell Q1 because the conductance of a MOSFETQ13 is small since it acts as a constant-current power source. As a power source voltage Vcc rises, the selection level of a word line comes higher than a comparatively high threshold voltage, by allowing the memory cell Q1 to be turned ON. Accordingly, the enhancing in conductance of the load MOSFETQ12 is limited. Therefore, the large drop of an output voltage V0 is compensated.</p>
申请公布号 JPS62195797(A) 申请公布日期 1987.08.28
申请号 JP19860037396 申请日期 1986.02.24
申请人 HITACHI LTD 发明人 FURUNO TAKESHI;NAKAI NOBUAKI;MATSUNO YOICHI;FUKUDA MINORU
分类号 G11C17/00;G11C16/06 主分类号 G11C17/00
代理机构 代理人
主权项
地址