| 摘要 |
PURPOSE:To speed up DMA transmission by adding a switching circuit to the titled circuit, and eliminating the competition between the DMA transmission and a refresh by substituting the refresh with DMA access. CONSTITUTION:A DMA-request signal 101 outputted from a DMA controlling circuit 1 enters the switching circuit 4. In case where the said signal 101 is a one to request of a depiction memory 17, a memory access cycle end signal 114 is outputted. When a value for the most significant address in an area of the memory 17 is outputted in a signal 102, the value is compared with the value of the most significant address of the memory 17 that is transferred beforehand from a depiction processor 3 through a depiction data bus 110 and stored in comparison registers 21-24 included in the switching circuit 4. Since the said two values are equal, a signal 114 is disabled at the end of the above described access cycle. And in the following access, a request signal 116 to a depiction memory 18 is outputted. In such a way, the refresh of the area in the memory 18 being accessed by the circuit 1 is substituted by a DMA access, eliminating an accessing from a refresh circuit 2.
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