| 摘要 |
PURPOSE:To decrease the number of pieces of elements and to integrate content calling memories by executing the storing action and the logical comparison action of one bit by using a pair of 3MOS-type memory cells. CONSTITUTION:The write action of a key information is executed in the unit of one bit, i.e., both read word lines RW00, RW10 are made in a high level, and a write signal is supplied from a data terminal D while the said lines RW00, RW10 are in the said state. Since a decoder YDCR forms a column selecting signal corresponding to one column when an address signal is supplied, common bit lines the inverse of CB, CB are coupled for instance with write bit lines WB00 and WB10. Also, as for a decoder XDCR, a signal from the terminal D is written in the pair of memory cells MC000 and MC100 because the selection level of a pair of write word lines X0, for instance, are in a high level. Thus, address signals are changed similarly, and the write bit line selected by the decoder XDCR is switched, so that a complementary signal made up of one-bit- share of bits is written through the terminal D as a key information.
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