| 摘要 |
PURPOSE:To strengthen the logic function without increasing the parasitic capacitance by designing the titled gate that lots of elements offering the logic function is disconnected from a bus line when the switching elements are set in the off-state, the high impedance state. CONSTITUTION:Transistors (TRs) Mps, Mns of a tri-state gate G3 provided with both a multi-input logic function and an output function of a tri-state by inserting MOS TRs Mps, Mns as switching elements to an operating power supply current path of a multi-input logic circuit G1 are connected to the output side of the circuit G1, and C-MOS TRs Mp1-Mn1, Mp2-Mn2 constituting the logic function of the circuit G1 to the power supply VCC side from the TRs Mps, Mns so as to disconnect the TRs constituting the logic function from the bus line LB when the TRs Mps, Mns are in the off-state, the high impedance output state. |
