| 摘要 |
PURPOSE:To shorten the access cycle time of a cache memory to improve the throughout of a system by providing a cache memory having plural memory banks, a cache controller, etc. CONSTITUTION:The address signal outputted from a CPU 1 onto a system bus 2 is supplied to a cache controller 4 and a cache memory 5 having plural memory banks, and the controller 4 decides whether required information is stored in the memory 5 or not. If it is stored there, a selecting signal of the memory bank corresponding to the address of information, a chip select signal, etc., are generated and are supplied to the memory 5. Data is read out from plural memory banks in the memory 5. In this case, only data read out from the desired bank is selected and outputted by the selecting signal or the like generated by the controller 4. Thus, the access cycle time of the memory 5 is shortened to improve the throughput of the system.
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