| 摘要 |
PURPOSE:To improve the processing speed by providing a memory cell array of even banks, that of odd banks, a shift circuit, etc., to access plural bits simultaneously on bit boundaries. CONSTITUTION:The address signal from an address latch circuit 12 is supplied to not only a memory cell array 17 through a row decoder 15 but also a column decoder 16A of even banks, a column decoder 16B of odd banks, and a shift circuit 26. The bit address signal which sets the extent of shift in the circuit 26 is supplied to the circuit 26 through a bit address signal line 28 and a bit address latch circuit 27. Thus, outputs of the memory cell array 17A of even banks and the memory cell array 17B of odd banks constituting the memory cell array 17 are supplied to the shift circuit 26 through decoders 16A and 16B and are shifted by a prescribed number of bits. As the result, data of one- word components of continuous bits is read and written regardless of word boundaries to increase the processing speed.
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