| 摘要 |
A decoder is described for a self-clocking code, e.g. a bi-frequency Manchester code. Transitions are detected in the encoded data and are clocked into a shift register by a clock having a frequency equal to a multiple of the data bit rate. A logic network is connected to the shift register so as to detect combinations of transitions representing encoded data bits "0" and "1". The logic network includes OR gate funnels which detect the transitions in a range of possible positions in the shift register, so as to allow for jitter in the input data signal. The circuit allows encoded data to be correctly decoded in the presence of jitter without the necessity for using a phase-locked loop. |
