发明名称
摘要 <p>PURPOSE:To reduce remarkably consuming electric power when power is to be saved at a C-MOS circuit device using single electric power source by a method wherein in the power having saving period, a FET to cut a current flowing into an external circuit from an input terminal or from an output terminal is inserted. CONSTITUTION:A P type channel MOS element Tr2, a load resistor R, an N type channel MOS element Tr1 are inserted in series between an electric power source VCC and the earth point. The element Tr1 and the resistor R function as an inverter, and make a supplied signal to the input terminal 13 to be reversed and to be outputted from the output terminal OUT. At normal operation, an ''L'' signal is applied to the input terminal on the gate side of the element Tr2 to make the element Tr2 to ON, and when power is to be saved, an ''H'' signal is applied to the terminal PS to make to OFF, and the electric power source current fed from the electric power source VCC is obstructed. By this output circuit, because the power source current flowed always in the external circuit at the traditional circuit can be cut when power is to be saved, consuming electric power can be reduced.</p>
申请公布号 JPS6239516(B2) 申请公布日期 1987.08.24
申请号 JP19810075889 申请日期 1981.05.20
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KAWADA TSUNEO
分类号 G06F1/32;G06F15/78;G11C11/409;G11C11/41;H01L21/8238;H01L27/092;H01L27/10;H01L29/78 主分类号 G06F1/32
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