| 摘要 |
PURPOSE:To specify a bus section where trouble occurs by providing a control means which is connected to a transmitting means and a receiving means connected to the bus section and tests transmission between bus sections. CONSTITUTION:A monitor signal control circuit CLR40 informs a bus arbitrating circuit (ABT) 10 of the interruption of the use of all frames or time slots assigned to a specific processor and transmits a test signal from a specific monitor signal circuit the frames or time slots whose use is interrupted while letting a specific monitor signal circuit receive the frames or time slots. When a fault section is investigated, the test signal is transmitted from the transmitting circuit (ASND) 311 closest to the start terminal of a bus dedicated to transmission and received by respective monitor signal circuits, thereby knowing the fault section.
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