| 摘要 |
PURPOSE:To execute the hard processing at a single hard processing circuit by providing the blanking part of an N1 bit at the terminator part and providing the delaying time difference of the N1 bit part for respective cameras, for an output signal outputted in parallel from plural image sensor cameras. CONSTITUTION:First, out of the output signal of an N0 bit from an image sensor 2 of the first camera 1, only an N1 bit at the terminator side is blanked, and shifted to the first shift register 4 and the second shift register 5 of an N0-N1 bit by a clock CK0 for driving the image sensor. For the second camera, since the shift register 4 comes to be 2N1 bits, the timing, in which the output signal of an N0-N1 bit is shifted to the second shift register 5, is delayed by an N1 bit more than the first camera. Then, simultaneously when an analog switch 6 of the first camera is closed, the analog switch 6 of the second camera is opened only when a clock CK0 for driving the image sensor of the N1 bit is counted, and the output signal of the N0-N1 bit is outputted to a hard processing circuit 7. The same processing is executed after the third camera. |
