发明名称 DUAL BYTE ORDER COMPUTER ARCHITECTURE
摘要 <p>A functional unit such as a CPU (10) follows one data ordering scheme internally, in which incoming and/or outgoing data pass through a data order conversion unit for realigning the data to a selectable external data ordering scheme. A means (28) for specifying the external data ordering scheme is accessible from outside the physical package(s) in which the functional unit is housed. The data order conversion unit may comprise a load aligner (20) and/or a store aligner (22), one or both of which may comprise means for shifting informational units of a smaller size within informational units of a larger size. The shift amount may derive from the low order address bits and may be altered depending on the external data ordering scheme selected.</p>
申请公布号 GR870205(B) 申请公布日期 1987.08.19
申请号 GR19870100205 申请日期 1987.02.06
申请人 MIPS COMPUTER SYSTEMS INC. 发明人 EBER LARRY B.;HANSEN CRAIG C.;RIORDAN THOMAS J.;PRZYBYLSKI STEVEN
分类号 G06F5/00;G06F7/00;G06F7/76;G06F12/04 主分类号 G06F5/00
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