| 摘要 |
<p>PURPOSE:To miniaturize a timing generating circuit applied to the control circuit of an electronic computer, etc. CONSTITUTION:This circuit is equipped with the delay circuit capable of extracting sequentially-delayed pulses from several taps, the circuit inputting a pulse appearing at any one tap of this circuit to the delay circuit again after a constant time, and the gate circuit operating at least from the appearance of a pulse at a minimum-delay time tap until the end of a pulse appearing at a maximum-delay-time tap, and signals appearing at the above-mentioned taps are supplied to the gate circuit, thereby extracting desired delay pulses by the logic output. This circuit consists of NAND circuits 13 to 25, 59, and 60, inverters 26 to 31, AND circuits 32 to 41 and 61, D type flip-flops 42 to 47, J-K flip-flops 48 to 51, and delay elements 52 to 58.</p> |
