<p>A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems. </p>
申请公布号
EP0232526(A2)
申请公布日期
1987.08.19
申请号
EP19860117604
申请日期
1986.12.17
申请人
HONEYWELL INFORMATION SYSTEMS INC.
发明人
JOYCE, THOMAS F.;MIU, MING T.;SHEN, JIAN-KUO;PHILLIPS, FORREST M.