| 摘要 |
<p>A level conversion circuit for converting CMOS logic level signals to ECL logic level signals includes: a level shift circuit (10) which receives as input a CMOS logic level signal and a CMOS logic level signal of opposite logic level to the first-mentioned CMOS logic level signal, and which supplies a base potential that effects operation of one of a pair of bipolar transistors (32, 34) in the unsaturated region and a base potential at which the bipolar transistor (32, 34) becomes non-conducting. A differential amplifier circuit (12) is connected between a ground terminal (G) and a low-potential voltage source (30) and selects the path of current flowing from the ground terminal (G) to the low-potential voltage source (30) under the control of the bipolar transistors (32, 34) whose emitter terminals are mutually connected and whose conduction is controlled by said base potentials. A bipolar transistor (14) is conduction controlled by one of the collector potentials of said bipolar transistors (32, 34) and outputs an ECL logic level signal from its emitter terminal. </p> |
