| 摘要 |
PURPOSE:To execute at a high speed the processing to unify plural vector data with a small bit width to one vector data with a large bit width by providing a special pipeline arithmetic unit. CONSTITUTION:At a vector processor, a pipeline arithmetic unit 200 is provided which receives two vector elements B(J) and C(J) and one scalar data S and process a logical calculation shown by [B(J)&S]1[C(S)&(S)] for one pipeline pitch. The pipeline arithmetic unit 200 outputs the calculating result of a program for one element each to one machine cycle and stores it through a signal line 23 to a register 430. Thus, in the conventional instruction, for example, four calculating instructions are required, and in the instruction, the processing can be executed by one calculating instruction and one arithemtic unit. |
