发明名称 |
MOS SEMICONDUCTOR DEVICE HAVING A FET AND A METAL WIRING LAYER |
摘要 |
An opening is formed at a position substantially midway along the widthwise direction of a wide metal wiring layer formed on a semiconductor substrate. A second metal wiring layer is formed in the opening in the same step for forming the wide first metal wiring layer. Drain electrodes of a CMOS inverter formed below the wide first metal wiring layer are connected to the second metal wiring layer through contact holes. The second metal wiring layer is connected to a polycrystalline silicon layer as an output wiring layer through a contact hole. |
申请公布号 |
EP0114382(B1) |
申请公布日期 |
1987.08.19 |
申请号 |
EP19830112993 |
申请日期 |
1983.12.22 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SAEKI, YUKIHIRO |
分类号 |
H01L21/8234;H01L21/3205;H01L21/82;H01L23/52;H01L23/528;H01L27/088;(IPC1-7):H01L23/52 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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