| 摘要 |
PURPOSE:To shorten the conversion time per range by providing a bypass and a selection circuit extracting a frequency division clock via the bypass and using the frequency division clock extracted by the selection circuit so as to apply A/D conversion. CONSTITUTION:When an AUTO signal for designating the automatic range mode is at a low level, a gate G4 is opened and the frequency division clock outputted from a FF 3 is given to a FF 4 and each frequency division circuit is used for bits of a counter. When the AUTO signal is at a high level, a gate G5 is opened, a frequency division clock outputted from a FFO is given to the FF 4 via a bypass BP and the frequency division circuits except the FF1-FF3 are used for bits of the counter. Thus, the number of bits of the counter is decreased by three, the time until the overflow or the conversion is finished is 1/8, the time required to find out a proper range after the range is switched is shortened. The AUTO signal is brought to the low level at the normal A/D conversion. Thus, the conversion time per range is shortened.
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