发明名称 FRAME PHASE SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To simplify a hardware constitution by providing a selection circuit writing a data in the unit of 2 frames and selecting a signal being a reference for the phase comparison from 2 kinds of write phase signals having a phase difference of 1 frame to an elastic memory. CONSTITUTION:An inputted data 101 enters the elastic memory 1 and is written by using a write phase signal 106 as a reference at first. The phase at a phase comparison circuit 3 is compared between the signal 106 and a read phase signal 105, and when the phase between them is overlapped, a write phase signal 107 delayed by one frame is selected by a selection circuit 2 and the data is written by using the phase signal 107 as a reference afterward. A write control signal 103 controlling whether or not the data is written controls how many bits are to be written in one frame. A control signal 104 controls whether or not the data is read, Thus, the hardware constitution is simplified and the number of ICs is reduced.</p>
申请公布号 JPS62188444(A) 申请公布日期 1987.08.18
申请号 JP19860030063 申请日期 1986.02.13
申请人 NEC CORP 发明人 FUNAE HIDEAKI
分类号 H04L7/027;H04L7/00 主分类号 H04L7/027
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