| 摘要 |
PURPOSE:To decrease the deviation of a picture by selecting the deviation between a horizontal synchronizing signal and a clock signal as a half period of the clock signal at maximum. CONSTITUTION:A clock signal S1 outputted from an oscillation circuit 1 is inputted to a data terminal D of a D flip-flop circuit 2 and one input of an exclusive OR circuit 3, and a horizontal synchronizing signal S2 is inputted to a clock terminal CK of the D flip-flop circuit 2. An output signal S4 of an exclusive OR circuit 3 rises without fail within a half period of the clock signal S1 from the leading edge of the horizontal synchronizing signal S2 and succeedingly, the output signal S4 of the exclusive OR circuit 3 repeats inversion in response to the clock signal S1. Since the timing of a picture processing circuit is set by a timing circuit 4 based on the output signal S4 of the exclusive OR circuit 3, the deviation of the synchronizing signal from the picture signal output side and from the picture signal input side is decreased more than a conventional circuit. Thus, the distortion of a picture due to the deviation of synchronization is reduced.
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