| 摘要 |
PURPOSE:To obtain a circuit with a minimized increase in the number of terminals necessary for testing a logical circuit, by detecting coincidence or non-coincidence between an output expected value from a memory means and an output pattern obtained by inputting into the logical circuit. CONSTITUTION:At a test, ROMs 1-4 and error detection circuits 7-8 are selectively specified by a ROM selection circuit 10 according to a selecting signal for ROM and logic to be tested to determine which logic should be tested and selectors 5 and 6 are set ready for testing by a normal/test switching signal from an input terminal S. Under such a condition, a clock is supplied to an address generation circuit and synchronizing this clock, addresses of specified ROM 1-4 selected are updated sequentially and test pattern corresponding to addresses inputted into logical circuits 22a 22b. The error detection circuits 7 and 8 compare actual outputs from the circuit 22a and 22b with output expected values from the ROMs 2 and 4 corresponding to the address to judge the coincidence or non-coincidence therebetwee. Then, the results (acceptance or reject) are outputted to an output terminal (E) thereby minimizing the increase in the number of input/output terminals. |
