| 摘要 |
<p>PURPOSE:To stop the output of a clock signal at an optional timing by counting up clock signals, comparing the counted value with an optional value and disconnecting a gate circuit by the compared output. CONSTITUTION:When signals obtained from a control switch 10 and a start switch 5 are turned to 'H' levels, a counter 4 counts up clock signals generated from clock oscillator 1 from the contents of all '0's. When the counted value exceeds a set value obtained from a terminal 7, the compared output of a comparator 6 is turned to the 'H' level and the outputs of an AND circuit 8 and an OR gate circuit 2 are turned to the 'H' levels. The output of an inverter 9 is turned to the 'L' level, a signal outputted from an enable terminal of the counter 4 is turned to the 'L' level, to hold the counted value and the output of the OR gate 2 is fixed on the 'H' level to stop a clock signal extracted from an output terminal 3. To restart the generation of a clock signal from the stopped state, a signal generated from the switch 10 is turned to the 'L' level.</p> |
