| 摘要 |
PURPOSE:To reduce the frequency of address generation for the arithmetic processing of the sum of products by alternately using two RAM address generating circuits for counting up and down addresses one by one. CONSTITUTION:At the storage of data Di in a data RAM 5, a switching circuit 26 selects a RAM address generating circuit 23. The circuit 23 generates addresses as a binary up counter increasing the addresses one by one. The prescribed number K of data Di inputted to a data input circuit 3 synchronously with clocks phi are successively stored in the addresses of the data RAM 5 specified by the values of the circuit 23. Since the data Di are read out from the RAM 5 at the arithmetic operation for the sum of products, the circuit 26 selects a RAM address generating circuit 7. At that time, the circuit 7 receives the number K of data Ei from the circuit 23. The circuit 7 generates the addresses of the RAM 5 as a binary down counter reducing the initial value K one by one.
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