| 摘要 |
PURPOSE:To realize a high-performance transistor with its source/drain gap reduced, source resistance greatly lowered, and mutual conductance high by a method wherein source/drain electrodes are located lower than the surface of a gate-carrying upper semiconductor layer constituting a heterojunction and extend into under the gate electrode. CONSTITUTION:A heterojunction is built of a high-purity or P-type first semiconductor layer 4 and a second semiconductor layer 2 with its electron affinity weaker than that of the first semiconductor layer 4. A gate electrode 1 is provided for controlling the number of carriers in an electron channel formed in the hetero interface and source/drain electrodes 6 are formed on both sides of the gate electrode 1, respectively. In such a field effect transistor the source/drain electrodes 6 are located under the surface of the second semiconductor layer 2 and extend into under the gate electrode 1. For example, on a semi-insulating GaAs substrate 5, a P<->-GaAs layer 4 is grown and, as a second semiconductor layer 2, a wafer is formed of an N-Al0.3Ga0.7As layer, N-AlxGa1-xAs layer, and N-GaAs layer, formed in that order. On the wafer, an Al- made gate electrode 1 is built. Ti, Au, Ge, and Ni are attached to the opening wherein source/drain regions are embedded, to be subjected to heat treatment for conversion into an alloy for the construction of source/drain electrodes 6. |
