| 摘要 |
PURPOSE:To reduce the resistance of a word line and the capacitance of a bit line and to operate the titled memory at high speed by a method wherein the word line is formed of polycrystalline Si, a first low resistance wiring is provided in parallel with the word line and connected to said word line in each memory cell, and the bit line is formed of a second low resistance wiring. CONSTITUTION:The section 4 shown by the slunt-lined part in diagram A is a first polycrystalline Si layer and it constitutes the cell plate of a capacitor. On the other hand, the slunt-lined section 6 in the diagram B is the first Al wiring layer, it runs in parallel with a second polycrystalline Si layer 5, and it is connected to the second polycrystalline Si layer 5 through the intermediary of a shunt aperture 12 on a shunt region 13'. Also, on an aperture part 14, a bit wire lead-out part 15 is formed using the first Al wiring layer. As the second Al wiring layer 8 is shown by the slunt-lined part in the diagram C, and it is turned to a bit line. The first Al wiring layer and the second Al wiring layer are connected at the black-painted part. |
