Parallel processing computer system with master and slave processors - has single instruction and multiple data channels in multiple architecture bus

摘要

The system has a number of similar processors all connected to a common MFA bus. One of the processors acts as a master, while the others are slaves which are activated, i.e. 'woken up', and controlled by the master processor. Individual memory units are connected to all processors. The designated master processor regularly carries out a self-test procedure. If a fault is detected, control is transferred to the next slave processor, which then becomes the master.