| 摘要 |
PURPOSE:To prevent the reduction in an operating speed of a selection circuit by providing a voltage level correction means to the output of a switch element and operating the voltage level correction means in the timing treated more than that of a control signal of a switch element control line. CONSTITUTION:An output is supplied by a wired OR 26, an output waveform is shaped by an inverter 27 and the output of a selection circuit 24 is extracted at an output line 24 by turning, e.g., a switch element 21 by a control line 22 among NMOS transistors (TRs) 21 connected respectively to plural input lines 20. Moreover, a clocked inverter 23 feeds back an output of the inverter 27 to correct the input voltage level of the inverter 27. A control line 25 applies a voltage retarded than a voltage 30 of the control line 22 as shown in the timing 31 to control the operation of the inverter 23. Thus, the reduction in the operating speed of the selection circuit is prevented in such a way. |
