| 摘要 |
PURPOSE:To execute the high speed of a cache access and the efficiency of an information processing system to adopt an MVS by outputting the data from a data array in which the coincidence is obtained at an AND circuit for the output of both comparator circuits. CONSTITUTION:When a certain logical address is given to a logical address register 1, a logical page address is given to an address converting mechanism 8 and simultaneously, address arrays 2 and 3 and a data array 7 are addressed. The output of an address array 2 is compared with the high order 18 bits of the logical page address and a comparing circuit 4, and the output of the address array 3 is compared with the physical page address and a comparator circuit 5. By the comparing of the comparing circuit 4, it is investigated whether the given logical address exists on the cache or not. When any comparator of 4a and 4b of the comparator circuit 4 is dissident, it is found to be a mishit. On the other hand, when either of the comparators of 4a and 4b is coincident, a hit and a mishit are decided by the output of comparators 5a and 5b to compare with the physical page address.
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