| 摘要 |
PURPOSE:To eliminate the need for a delay circuit with large scale even when a high speed logic element is employed by selecting the width of a clock signal larger than the sum between a clock signal skew DELTAt and a holding time th of the post-stage FF. CONSTITUTION:A delay circuit 31 is connected between the output of a FF 12 and an input of a FF 14. When a clock signal 18 descends, an input signal (data D1) 11 is inputted to the FF 12 at a point of time t1, an output signal 19 is obtained and a P-channel transistor (TR) 32 is turned off by the clock signal 18 inputted to the delay circuit 31 at the same time and an N-channel TR is turned off. Thus, the output signal 22 of the delay circuit 31 holds a level (data D0) just before the clock signal 18 descends. When a clock signal rises, a level (data D1) of the output signal 19 is outputted inversely at a point of time t2 as a delay output signal 22 and set to the FF 14 at the fall of the next clock signal 21. Thus, the output signal of the FF 12 is delayed by the clock pulse width, the holding time th is satisfied to guarantee the normal circuit operation. Thus, the delay of the clock signal width is obtained always and the circuit is constituted by the prescribed number of elements independently of the holding time th.
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