| 摘要 |
PURPOSE:To accelerate the transfer speed of an output buffer by increasing the gate width of an MOSFET of the final stage of a shift register larger by twice or more than that of an FET which forms the residual section. CONSTITUTION:In a front stage IC 14, an output buffer 11 has inverters 101, 103 of cascade two stages, and the final stage 30 of a shift register 1 has 4 transfer gates 31-34 and 4 inverters 35-38. An internal terminal 39 of th4e gates 31, 32 is connected with the inverter 34, and an internal terminal 39' of the inverters 37, 38 is connected with the inverter 101. The initial stage 40 of a rear stage IC 15 has 4 transfer gates 41 44, and 4 inverters. The output buffer receives an output of the stage 30 to drive a rear stage 15 through a terminal 12 and external wiring capacity 13. In this case, when the gate width of a C-FET which forms the final inverter 37 is increased twice or more than that of a C-FET which forms the residual section, the delay of the buffer 11 can be largely shortened to enhance the clock frequency of the entire system. |
