| 摘要 |
PURPOSE:To improve the read speed by shifting an output of a differential amplifier to an intermediate level as soon as an address of a storage cell is designated. CONSTITUTION:An edge trigger circuit detecting the edge of an address signal brings an edge trigger signal phi1 to a low level and a signal the inverse of phi1 to a high level, a PMOS 103 is turned on to short-circuit complementary outputs (a), (b) of the differential amplifier 1 and both the outputs reach a nearly same intermediate voltage. Binary information IN101, IN102 are inputted from the storage cell to the differential amplifier 1 based on the address signal and NMOSN101, N102 are turned respectively on/off, for example, then the complementary outputs (a), (b) start to go to a high and a low level respectively. Simultaneously, the signals phi1, the inverse of phi1 go respectively to a high and a low level, the PMOSP103 is turned off, a signal cut-off means 5 releases PMOSP108, NMOSN108 from the locking state and an output inverter 2 is inverted.
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