发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To obtain a stable oscillating frequency even when an input signal is disconnected by selecting an output signal of a switching circuit in response to the presence of an input signal so as to lock the phase of a voltage controlled oscillator to an input synchronizing signal or an oscillator output. CONSTITUTION:When an input signal (a) whose minimum level exists during the horizontal synchronizing period and whose level is zero between times T0 and T1 is inputted to an input terminal 1, a synchronizing detection circuit 2 separates a synchronizing signal (b), supplies it to a changeover circuit 3 and outputs a presence signal (e) of the input signal. Then an oscillator output signal (c) having the same frequency as that of the synchronizing signal (b) separated from the input signal (a) is inputted to the changeover circuit 3 from the oscillator 4. When the input signal (a) is disconnected, the changeover circuit 3 selects the oscillator output signal (c) and outputs it. Thus, even when the input signal (a) is disconnected, the sampling at a sampling circuit 6 is continued and the possibility of the decrease in the voltage held by a holding circuit 7 is precluded. Thus, the sampling holding signal (i) is kept constant except just after the input signal (a) is disconnected.
申请公布号 JPS62185411(A) 申请公布日期 1987.08.13
申请号 JP19860025838 申请日期 1986.02.10
申请人 NEC CORP;NEC ENG LTD 发明人 YASUDA TORU;HIRAI ICHIRO
分类号 H03L7/18;H03L7/06;H03L7/14 主分类号 H03L7/18
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