| 摘要 |
<p>An electrically erasable programmable logic array (EEPLA) (10,000) has an AND plane (10,002) having a first array (10) of devices (Md11 through MDMN) each containing nonvolatile upper and lower memory cells that each have two serially connected field effect transistors (STUC, MTUC and STLC, MTLC), and an OR plane (10.004) having a second array (12,600) of memory cells with each cell being the same as the cells of the first array (10), and output inverting buffers (12,400). Bit lines (BLa1 through BLaN) of the first array (10) are coupled to word lines (WL1a through WLNa) of the second array (12,600). Each bit line (BLf1 through BLfX) of the second array (12,600) is connected to an input terminal of an inverting buffer (12,400). The outputs of the inverting buffers (12,400) serve as the electrically erasable programmable logic array (10,000) output terminals. Each of the memory cells is an electrically erasable nonvolatile cell. This arrangement allows the EEPLAS (10,000) to be repeatedly reconfigured by an end user or by a run-time self adjusting reconfigurable control system. Various portions of EEPLAS (10,000) are illustrated in Figs. 3, 4, and 9.</p> |
