METHOD AND APPARATUS FOR REQUEUEING TRAPPED MICROADDRESSES IN A PIPELINED DATA PROCESSING SYSTEM

摘要

In a microprogrammed central processing subsystem, the apparatus and method for requeueing a sequence of microinstructions after the execution of the sequence is interrupted by identification and response to a trap condition includes a microinstruction address silo. Associated with each address is a tag field. The logic signal bit is asserted in the tag field position when a microinstruction address is selected from the decoder. When the trap return microinstruction is executed, on completion of the trap routine, and the first tag bit in the silo is asserted, then apparatus generates a Decoder Next signal as if this signal was generated by the trap return microinstruction and the addresses of the microinstruction stored in the silo are not used. If the first location in the silo does not have the tag bit asserted, then the contents of the silo are requeued to resume the original microprogram sequence until either an asserted tag bit is encountered or the silo is empty.