| 摘要 |
PURPOSE:To accelerate the operation of a semiconductor device by controlling the thickness of an oxide film of a polysilicon side wall of an emitter region to miniaturize an emitter/base separating width and an emitter slit width to reduce an external base and intrinsic base resistances, thereby decreasing a junction capacity CBE. CONSTITUTION:An N-type layer 4 and an N<+> type layer 6 are epitaxially formed by separating with SiO2 layer 5 and a P<+> type layer 3 on an N<+> type layer 2-buried P-type Si substrate 1, a P-type base layer 8 is superposed on the layer 4, and a 2-layer mask of an SiO2 layer 9, an Si3N4 layer 10 is formed. A polysilicon layer 12, an SiO2 layer 13, an Si3N4 layer 14 and an SiO2 layer 15 are superposed, selectively etched to expose the layer 9, and covered with an Si3N4 layer 17. Side wall oxide films 17a, 17b are formed by RIE. The film 9 is etched, an SiO2 film 18 is newly formed, etched to allow a film 18a to remain, a polysilicon film 19 and a resist film 20 are superposed and etched back. P-type ions are implanted to form an SiO2 layer 22, and a P<+> type layer 23 is formed. Then, the films 14, 13 are etched, N-type ions are implanted into the layer 12, an N<+> type layer 24 is formed, and base, emitter collector electrodes 26 28 are attached to complete a semiconductor device.
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